-- [并行语句] --

-- 1.信号赋值语句

entity test is
    port(
        a, b : in bit;
        s: in bit;
        y: out bit
        );
end entity test;

architecture one of test is
    signal yout : std_logic_vector(1 downto 0);
    signal a, b : std_logic;
    begin
        yout(1) <= a and b; -- 结构体内，进程外，为并行信号赋值
        yout(0) <= a or b;
end architecture one;

-- 省略赋值
signal d1 : std_logic_vector(4 downto 0);
d1 <= (1 => '1', 4 => '1', others => '0'); -- 结果：d1 == 10010

-- 2.条件信号赋值语句

y <= a when s = '0' else b;

-- 3.选择信号赋值语句（类似switch语句）

with s select
    y <= a when '0',
         b when others; -- when others 相当于其他情况

with s select
    y <= a when '0',
         b when '1',
         'X' when others;

-- 4.延时赋值语句

b <= reject 10 ns inertial a;   -- a的电平维持时间小于10ns，则变化被忽略

-- a的值延迟20ns后赋值给信号b, 以下两句等同
b <= a after 20 ns;
b <= inertial a after 20 ns;


-- 【process语句】 --
-- 结构体中进程和进程是并行的，进程内部是顺序执行的

-- a和b是敏感信号表，a或者b变化时，进行内部执行赋值语句
process(a, b)
begin
    yout(1) >= a and b;
    yout(0) >= a or b;
end process;

-- 同一信号进程内可以有多个驱动源，但只有最后一个被启动赋值；
-- 结果为：y = b; x = c - b;
signal a,b,c,x,y : integer;
process(a, b, c)
begin
    y <= a + b;  -- 不执行赋值；
    x <= c - y;   -- 执行赋值
    y <= b;      -- 执行赋值
end process;


-- 【block语句】 --

library ieee;
use ieee.std_logic_1164.all;

entity block_example is
    port(
        a, b : in std_logic;
        x, y : out std_logic;
    );
end block_example

architecture a of block_example is 
begin

    x_block: block(a = '1')
    begin 
        x <= guarded a xor b;
    end block;

    y_block: block
    begin
        y <= a or b;
    end block;

end architecture a;


-- 【component语句】 --

library ieee;
use ieee.std_logic_1164.all;
entity ord4l is 
    port(
        a1, b1, c1, d1: in std_logic, z1: out std_logic
    );
end entity ord4l;

architecture artord4l is
    component ND2   -- 元件说明语句
        port(a, b: in std_logic; c: out std_logic);
    end component ND2;
    
    signal a1, a2: std_logic;

begin
    u1: ND2 port map(a1, b1, s1);   -- 位置关联
    u2: ND2 port map(a => c1, c => s2, b => d1);    -- 名字关联
    u3: ND3 port map(s1, s2, c => z1);  -- 混合关联
end architecture artord4l;

-- 【generate语句】 --

entity Shift is
    port(sin, clk: in bit, sout: out bit)
end shift;

architecture Netlist of Shift is
    component dff
        port(d, clk: in bit, q: out bit);
    end component;
    signal z: bit_vector(0 to 4);
begin
    z(0) <= sin;
    qf: for i in 0 to 3 generate
        u1: dff port map(z(i), clk, z(i+1));
    end generate;
    sout <= z(4);
end Netlist;

